Performance Evaluation of Integrated Hard Real-Time Application and RISC V Processor for Spacecraft on Board Software Application - Y., Vishwanath; Desai, Kiran; Upendra, R S; Prasad, Venkatesh; Suvanam, Sasidhar Babu; Biradar, Arun; S., Supreeth; S., Rohith (International Journal of Intelligent Systems and Applications in Engineering, 2023)
Space industries operating critical missions and safety aspects must operate robust and error-free software systems. A trace amount of error causes failure of the entire spacecraft system; hence, the onboard software of spacecraft systems typically uses Baremetal Cyclic executives to maintain robustness under error-free conditions. Baremetal Cyclic executive software programs are highly predictable in their behavior, and have been evaluated and proven critically for space applications. Technology advent with increased computational power and concurrency necessitates high-end applications of spacecraft systems such as Agriculture, Weather forecasting, communication, and geospatial applications. To meet these challenges, spacecraft systems must be upgraded to handle high-level computational loads, time complexities, and parallelism in activity at the manifold. Currently, space agencies across the globe replace the conventional Baremetal Cyclic executives with advanced RTOS developed on single/multicore processors such as Power PC and LEON4 based on ARINC 653 specifications, which are proprietary, run with the operating system, that is, VxWorks, RTEMS, etc. The execution of the RISC V architecture in the onboard software of a spacecraft system offers advantages, such as openness, modularity, extensibility, and stability. Many RISC-V designs have single/multicore architectures with open-source RTOS support. In the present work, we developed a prototype built on hard real-time satellite application software and evaluated its performance using an RTOS stack on a RISC V series. This research also developed a library to allow portable application development for any flavor of the RISC V architecture.