Concurrent Computation Strategies: Unveiling the Power of Vedic Mathematics - Alaspure, Dinubhau B.; Dixit, Swati Rajesh; Edle, Jitendra S. (International Journal of Intelligent Systems and Applications in Engineering, 2023)
Within the dynamic realm of computational techniques, the fusion of age-old wisdom with contemporary technology has emerged as an intriguing frontier. This endeavor involves a profound investigation that combines the ancient wisdom of Vedic Mathematics with modern computing concepts. This innovative expedition not only reinvigorates conventional mathematical methodologies but also reveals the unexplored capabilities of simultaneous computation. The study presents the design and statistical analysis of a concurrent vedic multiplier architecture, suitable for various parallel computing applications, utilizing contemporary concurrent hardware architectures. This research study focuses on the multiplier architecture, which is the most hardware-intensive component. The ideas of Vedic mathematics are employed to define this architecture. The multiplier’s architecture is explained using the basic principles of Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The architecture is developed utilizing the latest High-Level Synthesis (HLS) Tool, such as Xilinx Vivado 2018.2. The architecture is designed to cater to various types of FPGA, including general-purpose, automotive, military, and high-reliability environments. Its primary objective is to ensure exact control over crucial characteristics such as delay, frequency, resources, and power..