Implementation of an Efficient and Reconfigurable Architecture for DCT on FPGA
Keywords:
DCT, FPGA, Transformations, Video ProcessingAbstract
The Discrete Cosine Transform (DCT) is computed to minimize the complexity of the algorithm without impacting the performance of the code. Several conventional DCT approximation techniques mainly concentrate on short transform lengths as well as some of them seem to be non-orthogonal. This research work provides an extensive recursive approach for orthogonal DCT approximation in which an estimated length of DCT can be obtained from a set of DC transforms length at the rate of input pre-processing additions. The suggested approximation concept is derived using recursive sparse matrix decomposition as well as by using symmetries of discrete cosine Transform basis vectors. The suggested approach is extremely scalable for the implementation of both hardware and software with DCT of various lengths and also this approach uses conventional 8-point DC transform approximation to obtain the estimated Discrete Cosine transform of any power of two lengths.The suggested DCT approximation performs well when compared to that of conventional DCT approximation approaches in terms of image/video compression also the suggested algorithm seems to have a reduced arithmetic challenge. We have presented a parallel architecture that is completely scalable and reconfigurable for computing approximate Discrete cosine Transform in this research work. The most significant aspects of the suggested architecture are that it can be designed to compute a 32-point DC transform or two 16-point DC transforms or four 8-point DC transforms simultaneously with negligible operating cost. The suggested design offers several benefits that are concerned with hardware intricacy, reliability as well as flexibility. These advantages are illustrated by the experimental outcomes that are obtained from the implementation of FPGA.
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