Optimized Full Swing Gate Diffusion Input Logic in Low Power Design
Keywords:
GDI, FSGDI, Low power, Boolean, VLSI, Minimum Energy operation PointAbstract
Power, delay and area optimized design techniques are consistently on high demand in semiconductor industry. Optimization techniques at system, architecture, gate and transistor levels are explored by researchers to combat the requirements of low power chips needed for industries. Grain level optimizations at gate and transistor levels offers higher reduction in power when compared with system and architectural levels. This paper focuses on optimization of Gate diffusion Input technique, a gate level approach for low power. This research presents the fact that Full Swing Gate Diffusion Input technique offers power, delay and area efficient circuits only for Boolean functions realized with a greater number of complemented literals rather than functions with true literals. This finding was verified by the implementation of Boolean functions exclusively comprising of true literals and complementary literals. The results depicted that Full Swing Gate Diffusion Input implementation is suitable only for Boolean functions comprising of complementary literals. For functions with true literals, the equations have to be modified to exploit the benefits of Full Swing Gate Diffusion Input techniques. The implementation was extended to realization of the state of the art 1-bit full adder, using conventional CMOS, direct FSGDI and modified FSGDI. On comparison with conventional CMOS full adder, modified FSGDI with more complementary literals presented a significant 86% reduction in Power Delay Product when compared with direct FSGDI full adder that presented 23% reduction. Maximum reduction of power in FSGDI circuits can be realized when the circuits are modified for implementation with complementary literals.
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Morgenshtein, A. Fish, and I. A. Wagner, “Gate-diffusion input (GDI): A power-efficient method for digital combinatorial circuits,” IEEE Trans. Very Large Scale Integr. Syst., 2002 doi: 10.1109/TVLSI.2002.801578.
Morgenshtein, A., Shwartz, I., Fish, A.: ‘Gate-diffusion input (GDI) logic instandard CMOS na-noscale process’. Proc. IEEE 26th Conv. of Electri-cal andElectronics Eng., Eliat, Israel, 2010, pp. 776–780
E. Abiri, A. Darabi, and A. Sadeghi, “Gate-diffusion input (GDI)method for designing energy-efficient circuits in analogue voltage-mode fuzzy and QCA systems,” Microelectronics J., 2019. doi: 10.1016/j.mejo.2019.04.001.
R. Uma and P. Dhavachelvan, “Modified Gate Dif-fusion Input Technique: A New Technique for En-hancing Performance in Full Adder Circuits,” Proce-dia Technol., 2012. doi: 10.1016/j.protcy.2012.10.010.
Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, “Full-swing gate diffusion input logic - Case-study of low-power CLA adder design,” Integr. VLSI J., 2014. doi: 10.1016/j.vlsi. 2013.04.002.
R. Uma, J. Ponnian, and P. Dhavachelvan, “New low power adders in Self Resetting Logic with Gate Diffusion Input Technique,” J. King Saud Univ. - Eng. Sci., 2017. doi: 10.1016/j.jksues.2014.03.006.
S. Radhakrishnan, T. Nirmalraj, and R. kumar karn, “An enhanced Gate Diffusion Input technique for low power applications,” Microelectronics J., 2019. doi: 10.1016/j.mejo.2019.104621.
Geetha S. and Amritvalli P. ,”Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique,” J. Electron.Test.35, 3 (June 2019), 383–400. DOI: https://doi.org/10.1007/s10836-019-05802-2
Abiri, E., Darabi, A., Salehi, M.R. et al.(2020). Opti-mized Gate Diffusion Input Method-Based Reversi-ble Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II. Circuits Syst Signal Process 39, 4516–4551. https://doi.org/10.1007/s00034-020-01382-1
M. Hasan, H. U. Zaman, M. Hossain et al., Gate Diffusion Input technique based full swing and scal-able 1-bit hybrid Full Adder for high performance applications, Engineering Science and Technology, an International Journal, https://doi.org/10.1016/j.jestch.2020.05.008
Saji, J., Kamal, S.: ‘GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology’, Microprocess. Microsyst., 2017, 49, pp. 18–27. https://doi.org/10.1016/j.micpro.2017.01.004
Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, High-efficient and error-resilient gate diffusion in-put-based approximate full adders for complex mul-tistage rapid structures, Computers and Electrical Engineering, Volume 109, Part A, 2023,108776, ISSN 0045-7906, https://doi.org/10.1016/j.compeleceng.2023.108776.
Forouzan Bahrami, Nabiollah Shiri, Farshad Pe-saran, Imprecise Subtractor Using a New Efficient Approximate-Based Gate Diffusion Input Full Ad-der for Bioimages Processing., Computers and Elec-trical Engineering, Volume 108, 2023, 108729, ISSN 0045-7906. https://doi.org/10.1016/j.compeleceng.2023.108729.
Deymad SF Shiri N Pesaran F. High-efficient re-versible full adder realized by dynamic threshold-based gate diffusion input logics. Microelectronics journal. 2023. doi:10.1016/j.mejo.2023.105972
Anuja A Girdharilal A. Low power low area digital modulators using gate diffusion input technique. 2019:245-252. doi:10.1016/j.jksues.2017.08.001
Mahmood R Yaqhoub S Nabiollah S Ayoub S, An approximate cntfet 4:2 compressor based on gate diffusion input and dynamic threshold. 2021:650-652. doi:10.1049/ell2.12221
Biswarup Mukherjee and Aniruddha Ghosal, Design of a low power, double throughput cyclic combina-tional gate diffusion input based radix-4 MBW mul-tiplier and accumulator unit for on-chip RISC pro-cessors of MEMS sensor, 2019 J. Micromech. Mi-croeng. 29 064003. DOI 10.1088/1361-6439/ab1504
Hussain I Chaudhury S. Fast and high-performing 1-bit full adder circuit based on input switching activi-ty patterns and gate diffusion input technique. Cir-cuits systems and signal processing. 2020:1762-1787. doi:10.1007/s00034-020-01550-3
Abiri E Darabi A. Design of low power and high read stability 8t-sram memory based on the modified gate diffusion input (m-gdi) in 32 nm cntfet technol-ogy. Microelectronics journal: part a.:1351-1363. doi:10.1016/j.mejo.2015.09.016
Abiri E Darabi A Salem S. Design of multiple-valued logic gates using gate-diffusion input for image pro-cessing applications. Computers and electrical engi-neering. 2018:142-157. doi:10.1016/j.compeleceng.2018.05.019
Rafiee, M., Sadeghi, Y., Shiri, N. and Sadeghi, A. (2021), An approximate CNTFET 4:2 compressor based on gate diffusion input and dynamic thresh-old. Electron. Lett., 57: 650-652. https://doi.org/10.1049/ell2.12221
Sadeghi, R. Ghasemi, H. Ghasemian and N. Shiri, "High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Archi-tectures," in IEEE Embedded Systems Letters, vol. 15, no. 1, pp. 33-36, March 2023.doi: 10.1109/LES.2022.3192530.
Zahra Zareei, Mehdi Bagherizadeh, Moham-madHossein Shafiabadi, Yavar Safaei Mehrabani, Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems, Microelectronics Journal, Volume 108, 2021, 104962,ISSN 0026-2692. https://doi.org/10.1016/j.mejo.2020.104962.
Garg, Ankit, and Garima Joshi. "Gate diffusion input based 4‐bit Vedic multiplier design." IET Circuits, Devices & Systems 12.6 (2018): 764-770.
R. Yadav and M. Kumar, "Implementation of 4×4 Fast Vedic Multiplier using GDI Method," 2020 In-ternational Conference on Electrical and Electronics Engineering (ICE3), Gorakhpur, India, 2020, pp. 527-529. doi: 10.1109/ICE348803.2020.9122890.
Baluprithviraj Krishnaswamy Natarajan, Vi-jayachitra Senniappan, Logic obfuscation technique using configurable gate diffusion input for improved hardware security, IEICE Electronics Express, 2018, Volume 15, Issue 19, Pages 20180802, Released on J-STAGE October 10, 2018
Sanapala, K. and Sakthivel, R. (2019), Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems. IET Cir-cuits Devices Syst., 13: 465-470. https://doi.org/10.1049/iet-cds.2018.5559
Calhoun B. H., Wang A., and Chandrakasan A. (2005). Modeling and sizing for minimum energy operation in subthreshold circuits” doi: 10.1109/JSSC.2005.852162
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