Pseudo-Differential Tow-Thomas Biquad Architecture based Low Power and Low Area Analog Filter for 5G Applications
Keywords:
Analog filter, Complementary metal oxide semiconductor, High voltage threshold transistor, Pseudo-differential Tow-Thomas Biquad architecture, Power consumption.Abstract
Analog filters are used in huge number of integrated circuit designs such as radio frequency transceivers, global system for mobiles and wireless applications. The development of low power analog filter is a challenging task for communication applications, especially 5G communications. In this paper, a Pseudo-Differential Tow-Thomas Biquad (PDTTB) architecture for analog filter is proposed in Complementary Metal Oxide Semiconductor (CMOS) 45 nm technology for minimizing the size of transistors. The buffer incorporated in the designed PDTTB based low power and low area Analog Filter namely PDTTB-AF is used to avoid the degradation of signal in filter output. The High Voltage Threshold (HVT) transistor is developed in ring oscillator for minimizing the power consumption. The HVT transistor in analog filter has less subthreshold currents and reduces the leakage current. Moreover, the phase detector and charge pump are also designed with less number of transistors where HVT is used to minimize the power consumption in the filter. The main objective of this proposed architecture is to minimize the power consumption by using the less number of transistors which helps to develop area efficient filter. The proposed architecture is evaluated with area, delay, frequency, power and Figure-of-Merit (FoM). The existing research namely Low Voltage Mixed Mode (LVMM)-AF is used to evaluate the performances of PDTTB-AF architecture. The power consumption of PDTTB-AF architecture is 61.16uW which is lesser than that of LVMM-AF.
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