Development Of A 33 Ghz Low Noise Amplifier Utilizing The Multigate Technique For Cascode Devices
Keywords:
mm-wave · RF · LNA · Receiver · 5G · Multi-gate · Communication systems · CMOS · SOIAbstract
The presence of increased parasitic components in silicon-based nanometer (nm) scale active devices results in various performance trade-offs when optimizing key parameters, such as maximum frequency of oscillation (fmax), gate resistance, and capacitance, among others. A common-source cascode device is frequently employed in amplifier designs operating at RF/millimeter-wave (mmWave) frequencies. Besides intrinsic parasitic components, extrinsic components arising from wiring and layout effects are also vital for the performance and precise modeling of these devices. This study presents a comparison of two distinct layout techniques for cascode devices aimed at optimizing extrinsic parasitic elements, including gate resistance. A multi-gate or multi-port layout technique has been proposed to optimize gate resistance (rg). Measurement results indicate a 10% reduction in rg for the multi-gate layout technique when compared to a conventional gate-above-device layout for cascode devices. Nevertheless, the conventional layout demonstrates smaller gate-to-source and gate-to-drain capacitances, resulting in enhanced performance regarding speed, specifically fmax. An LNA has been designed to operate at a frequency of 33 GHz utilizing the proposed multi-gate cascode device. The LNA achieves a measured peak gain of 10.2 dB and a noise figure of 4.2 dB at 33 GHz. All structures have been designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technolog.
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