A Novel Ultra Low Power and Highly Stable SRAM Bit-Cell for High-Speed Applications Using 45nm Technology Node
Keywords:
SRAM Cell, Static Noise Margin, Read Delay, Write Delay, Leakage power.Abstract
Modern system-on-chip applications demand SRAMs that not only operate at high speeds and offer robust stability but also prioritize energy efficiency for prolonged functionality. In this research, various SRAM cell architectures are explored, with particular emphasis on a newly proposed 9T SRAM bit-cell. Key parameters analyzed include leakage power, read and write delays, and static noise margins (WSNM and RSNM). Simulation outcomes indicate that the proposed 9T SRAM cell achieves the highest RSNM among all layouts, while the 8T SRAM cell records superior WSNM, attributed to its use of p-type access transistors. Furthermore, the 8T cell delivers reduced write delays when compared to the other designs. Notably, the 9T SRAM cell also demonstrates the lowest leakage power across all examined topologies. The fabrication of these SRAM bit cells was carried out using gpdk 45nm technology in the Cadence Virtuoso environment.
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Copyright (c) 2025 Tejas D. Darji, Devendra R. Patel, Hiren J. Vasava, Richa A. Choubey, Yogin G. Garasia, Patel Kundanben Amrutlal
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