Transactional Memory: A Comprehensive Review of Implementation, Applications, Performance, Challenges, Framework Comparisons, and Future Prospects
Keywords:
Concurrency Management, Nested Transactions, Parallel Programming, Software Transactional Memory (STM), Transactional Memory (TM)Abstract
Transactional Memory (TM) offers a high-level synchronization abstraction for parallel programming, improving scalability, reliability, and productivity. It addresses challenges in multicore and distributed systems, surpassing traditional methods like locks and semaphores. TM implementation strategies—Software Transactional Memory (STM), Hardware Transactional Memory (HTM), and Hybrid Transactional Memory (HyTM)—present trade-offs in performance, scalability, and adaptability, catering to diverse workloads. Advanced features, including Nested Transactions, enhance fault tolerance and minimize rollback costs through modular transaction management.TM’s lock-free synchronization finds applications in concurrent data structures, graph algorithms, scalable systems, and real-time computing, boosting reliability and system performance. Performance analyses of STM, HTM, and HyTM highlight their strengths and limitations in handling varying workloads. However, challenges persist, such as programming model integration, contention management, and efficiently managing large or nested transactions. Innovations like Dynamic STM, Adaptive Conflict Resolution, and extended HTM support tackle these issues, advancing TM capabilities. Frameworks such as TCC and LogTM, along with STM and HTM implementations, illustrate TM's evolution. Future research aims to overcome current limitations, ensuring TM’s role in high-performance computing, real-time systems, and large-scale data processing. TM simplifies synchronization, empowering parallel programming to meet modern and future system requirements efficiently.
Downloads
References
H. Grahn, “Transactional memory,” Journal of Parallel and Distributed Computing, vol. 70, no. 10, pp. 993-1008, 2010.
J. B. K. C. L. K. R. a. Y. Z. J. R. Blumofe, “Cilk : An efficient multithreaded runtime system,” Journal of Parallel and Distributed Computing, vol. 37, no. 1, pp. 55-69, August 1996.
P. B. a. N. Goodman, “Concurrency Control in Distributed Database Systems,” ACM Computing Surveys, vol. 13, no. 2, p. 185 – 221, 1981.
R. a. M. M. S. Alexandru Turcu, “ On closed nesting in distributed transactional memory,” in Seventh ACM SIGPLAN workshop on Transactional Computing, 2012.
J. R. L. a. R. R. T. Harris, Transactional Memory, 2 ed., Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, 2010, pp. 1-247.
M. H. a. J. E. B. Moss, “Transactional memory: architectural support for lock-free data structures,” in Proceedings of the 20th annual international symposium on Computer architecture (ISCA '93)., May 1993.
N. &. T. D. Shavit, “Software transactional memory,” in Proceedings of the 14th Annual ACM Symposium on Principles of DistributedComputing, Ottawa, Can, 1995.
T. L. V. M. B. R. M. B. S. a. T. S. Ali-Reza Adl-Tabatabai, “Compiler and runtime support for efficient software transactional memory,” in Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada , 2006.
S. Peyton-Jones, Beautiful concurrency, A. O. a. G. Wilson, Ed., O'Reilly, 2007.
F. Y. L. V. L. M. M. D. N. Peter Damron, “Hybrid transactional memory,” in Proceedings of the 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006.
J. E. B. Moss, “Nested Transactions: An Approach to Reliable Distributed Computing,” Ph.D. Thesis, Technical Report MIT/LCS/TR-260,MIT Laboratory for Computer Science, Cambridge, MA, April 1981.
T. a. B. Ravindran, “ On open nesting in distributed transactional memory,” in 5th Annual International Systems and Storage Conference (SYSTOR) ’12, 2012.
S. M. A.-R. A.-T. A. L. H. R. L. H. J. E. B. M. S. a. T. S. Y. Ni, “Open nesting in software transactional memory,” in PPoPP ’07: Proceedings of the 12th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming ,ACM Press, New York, NY, USA, 2007.
N. C. J. Diegues, “Review of nesting in transactional memory,” Tech. rep., Technical Report RT/1/2012, Instituto Superior Técnico/INESC-ID , 2012.
T. H. a. S. Stipic, “Abstract nested transactions,” in Second ACM SIGPLAN Workshop on Transactional Computing, 2007.
L. H. J. Eliot B. Moss, “Nested transactional memory: Model and architecture sketches,” Science of Computer Programming, vol. 63, no. 2, pp. 186-201, 2006.
M. S. C. H. A. A. D. E. W. S. I. a. M. S. V. Marathe, “Lowering the overhead of Software Transactional Memory,” in 1st ACM SIGPLAN Workshop on Transactional Computing (TRANSACT '06), 2006 .
M. &. L. V. &. M. M. &. S. W. Herlihy, “ Software Transactional Memory for Dynamic-Sized Data Structures,” in Proceedings of the Annual ACM Symposium on Principles of Distributed Computing, 2003.
A.-R. A.-T. R. H. C. C. M. a. B. H. B. Saha, “McRT-STM: a high-performance Software Transactional Memory system for a multi-core runtime,” in SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'06), 2006.
M. S. a. M. S. L. Dalessandro, “NOrec: Streamlining STM by abolishing ownership records,” in Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '10), 2010.
J. B. M. M. M. H. a. D. W. K. Moore, “LogTM: log-based transactional memory,” in Proceedings of the 12th High-Performance Computer Architecture International Symposium (HPCA '06), 2006.
J. B. K. E. M. L. Y. M. D. H. B. L. M. M. S. a. D. M. J. Moravan, “Supporting Nested Transactional Memory in LogTM,” in 12th International Conference on Architectural Support for Programming Languages and Operating Systems in SIGPLAN Notices (Proceedings of the 2006 ASPLOS Conference), 2006.
R. C. Ammlan Ghosh and Haskell, Implementing Software Transactional Memory using STM, vol. 2, Advanced Computing and Systems for Security ,Springer AISC, 2016, pp. 235-248.
M. R. Y. a. M. F. Le, “Revisiting software transactional memory in Haskell,” ACM SIGPLAN Notices, vol. 51, no. 12, pp. 105-113, 2016.
Du Bois, “An Implementation of Composable Memory Transactions in Haskell,” in Software Composition, SC 2011,Lecture Notes in Computer Science,Springer, Berlin, Heidelberg., 2011.
H. T. M. S. J. S. S. S. Discolo, “Lock Free Data Structures Using STM in Haskell,” in Functional and Logic Programming, FLOPS , 2006.
M. L. V. &. M. M. Herlihy, “A flexible framework for implementing software transactional memory,” ACM SIGPLAN Notices, vol. 41, no. 10, pp. 253-262, 2006.
S. M. S. P. J. a. M. H. T. Harris, “Composable memory transactions,” in Proceedings of the Tenth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP ’05, Chicago, IL, USA, 2005.
G. a. S. F. S. Peyton Jones, “Concurrent Haskell,” in 23rd ACM Symposium on Principles of Programming Languages (POPL’96), 1996.
M. H. C. J. C. C. M. C. K. a. K. O. B. Carlstrom, “The ATOMOS Transactional Programming Language,” in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'06), 2006.
N. B. C. K. a. K. O. W. Baek, “Implementing and evaluating nested parallel transactions in software transactional memory,” in Proceedings of the 22nd ACM Symposium on Parallelism in Algorithms and Architectures, SPAA ’10,, Thira, Santorini, Greece, 2010.
R. K. a. K. Vidyasankar, “HParSTM: A Hierarchy-based STM Protocol for Supporting Nested Parallelism,” in 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT '11), 2011.
W. A.-R. A.-T. T. S. X. T. a. R. N. H. Volos, “NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems,” in Proceedings of the 23rd European Conference on Object-Oriented Programming(ECOOP '09), 2009.
J. T. F. a. J. S. K. Agrawal, “Nested parallelism in transactional memory,” in Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '08), 2008.
D. P. F. R. G. a. M. K. J. Barreto, “ Leveraging parallel nesting in transactional memory,” in Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '10).
H. R. a. E. Witchel, “The xfork in the road to coordinated sibling transactions,” in 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT '09), 2009.
C. O. S. U. E. A. F. G. B. S. M. V. Tim Harris, “ Transactional Memory: An Overview,” IEEE Micro , vol. 27, no. 3, pp. 8-29, 2007.
L. H. a. V. W. a. M. K. C. a. B. D. C. a. J. D. D. a. B. H. a. M. K. P. a. H. W. a. C. K. a. K. Olukotun, “Transactional Memory Coherence and Consistency,” in 31st Annual International Symposium ,Computer Architecture(ISCA04), 2004.
N. M. a. J. N. A. S. R. Cordeiro, A Review of Hardware Transactional Memory, 10th Workshop on Parallel and Distributed Processing (WSPPD), 2012.
J. CHOQUETTE, G. TENE and K. NORMOYLE, “Speculative multiaddress atomicity”. US Patent 7,376,800.
Click., Azul's experiences with hardware transactional memory, 2009.
R. C. M. E. M. K. A. L. S. Y. H. Z. a. M. T. Shailender Chaudhry, “Rock: A High-Performance Sparc CMT Processor,” IEEE Micro, vol. 29, no. 2, pp. 6-16, 2009.
Y. L. M. M. a. D. N. D. Dice, “Early experience with a commercial hardware transactional memory implementation,” in 14th international conference on Architectural support for programming languages and operating systems,ASPLOS, New York, USA, 2009.
P. Bright, “IBMs new transactional memory: Make-or-break time for multithreaded revolution,” ARS Technica, 2011.
M. G. P. W. M. O. J. N. A. C. B. R. S. a. M. M. M. A. Wang, “Evaluation of blue gene/q hardware support for transactional memories,” in 21st International Conference on Parallel Architectures and CompilationTechniques, PACT ’12, Minneapolis, MN, USA, 2012.
J. Reinders, “Transactional synchronization in Haswell,” Intel Software Network , 2012.
G. A. Asi, “Performance Tradeoffs in Software Transactional Memory,” Master Thesis Computer Science, School of Computing Blekinge Institute of Technology, No:MCS-2010-28, Sweden, May 2010.
O. S. N. S. Dave Dice, “ Transactional Locking II,” in 20th International Symposium on Distributed Computing, Stockholm,Sweden, 2006.
F. a. T. R. Pascal Felber, “Dynamic performance tuning of word-based software transactional memory,” in 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming (PPoPP '08), New York, USA, 2008.
R. G. a. M. K. A. Dragojevic, “Stretching transactional memory,” in ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Dublin, Ireland, 2009.
S. Classen, “LibSTM: A fast and flexible STM Library,” Master's Thesis, Laboratory for Software Technology, Swiss Federal Institute of Technology, ETH Zurich, Feb, 2008.
I. a. M. Raynal, “A Lock-Based STM Protocol That Satisfies Opacity and Progressiveness,” in Proceedings of the 12th International Conference on Principles of Distributed Systems (OPODIS'08, 2008.
W. N. S. I. a. M. L. Scott, “Contention Management in Dynamic Software Transactional Memory,” in Proceedings of the ACM PODC Workshop on Concurrency and Synchronization in Java Programs, Canada, July 2004.
N. S. a. M. L. S. y, “Advanced contention management for dynamic software transactional memory,” in Proceedings of the twenty-fourth annual ACM symposium on Principles of distributed computing, Las Vegas, NV, USA, 2005.
e. a. R. Guerraoui, “Toward a theory of transactional contention managers,” in Proceedings of the twenty-fourth annual ACM symposium on Principles of distributed computing, Las Vegas, NV, USA, 2005.
M. L. Scott, “Applications Included with RSTM WebPage,” [Online]. Available: http://www.cs.rochester.edu/research/synchronization/rstm/applications.shtml.
Downloads
Published
How to Cite
Issue
Section
License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.
All papers should be submitted electronically. All submitted manuscripts must be original work that is not under submission at another journal or under consideration for publication in another form, such as a monograph or chapter of a book. Authors of submitted papers are obligated not to submit their paper for publication elsewhere until an editorial decision is rendered on their submission. Further, authors of accepted papers are prohibited from publishing the results in other publications that appear before the paper is published in the Journal unless they receive approval for doing so from the Editor-In-Chief.
IJISAE open access articles are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License. This license lets the audience to give appropriate credit, provide a link to the license, and indicate if changes were made and if they remix, transform, or build upon the material, they must distribute contributions under the same license as the original.